1. Field of the Invention
The present invention is directed to a method for locating a synchronization sequence S having a length s in a serial bit stream, and an arrangement for the implementation of such a method.
2. Description of the Prior Art
In many instances, the transmission of digital data requires a frame structure of the data. In order to save connecting lines, no frame start signal is transmitted given the transmission of the data from ASIC to ASIC. The receiver ASIC must then determine the frame start from the data stream.
For locating an n-bit long synchronization sequence in a serial bit stream, it is known to search bit-by-bit in the serial data and to undertake a comparison to the entire synchronization sequence. This requires a high realization outlay with a high logic depth and a long latent time until the recognition of the word boundary in the data stream.
An object of the invention is to provide a method and a computer-readable data carrier available with which a synchronization sequence can be located faster in a serial bit stream and with lower realization outlay, particularly less silicon area and lower dissipated power.
The above object is achieved in accordance with the principles of the present invention in a first version of a method for locating a synchronization sequence in a serial bit stream, wherein the synchronization sequence is defined as being composed of a first word with a prescribable first length and at least one second word with a prescribable second length, wherein a first comparison of the first word is undertaken to an arbitrary bit sequence of the serial bit stream having the first length, and jumping to a second repetition if the first word agrees with this bit sequence, executing a first repetition of the comparison of the first word to a bit sequence shifted by one bit compared to the previously compared bit sequence, if the first word does not agree with the previously compared bit sequence, executing a second repetition of the comparison of the first word to a bit sequence shifted by one bit relative to the previously checked bit sequence until a bit sequence shifted by the second length is checked, executing a first return jump to the second repetition as soon as coincidence is found in one of the executions of the second repetition, undertaking a second comparison as to whether the second word coincides with the bit sequence shifted by the second length, and executing a second return jump to the first repetition if no coincidence is found in the second comparison, and otherwise ending the method.
In a second version of the method, the synchronization sequence is defined as containing three or more words, and an additional execution is inserted for each further word between the step of the second return jump and the end, with each additional execution corresponding to the steps beginning with the second repetition up to and including the second return jump, but with a further word, having a further length, being used instead of the second word and the second length.
The inventive method makes it possible for the search in the serial bit stream to relate only to a word length a, b rather than to the entire length s of the synchronization sequence. When a word A, B has been recognized, the expected value for the search for the next word A, B is set by a controller. This method of word-by-word recognition offers several advantages. For example, only very short latent times are required until the recognition of the word boundaries in the data stream. Additionally, the realization outlay is lower compared to bit-by-bit recognition, since a shorter comparison sequence (only respectively one word) is used, which leads to less of a logic depth. Also, the expected values for the words A, B to be searched are programmable, and thus can be freely defined for each application, and thus can be selected in an application-specific manner. When an inventive method is implemented with an arrangement that comprises an integrated circuit, then silicon area and dissipated power are saved.